1. Field of the Invention
The present invention is directed to a method and a device for analyzing a failure in a semiconductor wafer on which a plurality of chips having a plurality of memory cells are formed, and especially to a failure analysis method and device employing a fail bit map (hereinafter referred to as a FBM).
2. Background of the Invention
A well-known method for analyzing a failure in a semiconductor wafer, on which a plurality of semiconductor chips having a plurality of memory cells (generally arranged in a matrix of rows and columns) are formed, is the one employing a tester (known also as a LSI tester). In this method, electrical characteristics of all the memory cells in the semiconductor wafer are tested, and a failure detected therein is displayed on the FBM indicating a position of a defective memory cell (bit), in a space defined by coordinates including X-coordinates extending along a line direction and Y-coordinates extending along a column direction. This FBM is used to infer the cause of failure. A defective bit is called a failure bit.
However, the use of the FBM gives only a position of failure and information as to an electrical abnormal phenomenon, that is, a failure phenomenon, for example, on where and what (such as leak, open, and short) occurs. Namely, the cause of failure is not directly indicated. Thus, only the use of the FBM is not enough to infer the cause of failure in the field of manufacture or inspection, so that it is necessary to define the cause responsible for the failure phenomenon in a manufacturing process.
One of the well-known methods proposed on the basis of this idea is disclosed in the Japan Patent Laid-Open Gazette No. P06-275688A. In this method, a defect inspection system is used to obtain a physical inspection result, such as a dust particle or defect on a surface of the semiconductor wafer (hereinafter generally referred to as a "defect" throughout this specification, which is likely to be the cause of failure), for each step of a manufacturing line including a plurality of steps. Simultaneously, electrical characteristics of each memory cell in the semiconductor wafer manufactured through the manufacturing line are tested by a tester. Then, the FBM obtained from this test result and the physical inspection result of the position of a defect for each step are compared to infer which step of the manufacturing process generates a defect to be the cause of failure.
The above comparison between the FBM and the inspection result is made by retrieving a defect existing within a predetermined tolerable range whose center is each failure belonging to the FBM, from the defects obtained for each step by the defect inspection system. If the tolerable range is an appropriate size, a defect existing therein is assumed to be the cause of failure. With respect to each failure of the FBM, as the position of the failure in the FBM is closer to the position of the defect obtained by the defect inspection system, the possibility of the defect being the cause of failure is getting larger.
FIG. 3 shows the FBM when a memory cell array to be analyzed in the semiconductor wafer consists of, for example, 100.times.100 memory cells, and FIG. 4 is a detail view showing the vicinity of an origin 0 of the FBM shown in FIG. 3. The black portion of FIG. 4 indicates a failure bit. Since data of the FBM shown in FIG. 3 forms a considerable number, the FBM in which data is compressed is used for a conventional analysis. FIG. 5 shows the FBM after compressing the FBM of FIG. 3. In FIG. 5, the FBM of FIG. 3 is divided into blocks of 10.times.10 bits in X and Y directions, respectively. A block including a failure bit is called a failure block, indicated by the black portion of FIG. 5.
However, when a plurality of failure blocks are clustered like in the vicinity of the origin 0 of FIG. 5, it is impossible to determine correct coordinates of a defect to be the cause of failure. This results in low reliability of the comparison between the failure block and the defect.